FIELD PROGRAMMABLE LOGIC ARRAY BASED CASCADABLE N-BIT MAGNITUDE COMPARATOR
This paper is an analytical presentation of the design of an n-bit cascadable digital magnitude comparator (CDMC). The combination of three or more CDMCs in series in some possible problem situations suffers significantly in propagation delay. To minimize this, substantial research efforts have been devoted to developing CDMC using different approaches. This work proposes to use field programmable logic array (FPLA) in the realization of CDCM. Starting from the entered variable (EV) truth-table of the considered 4-bit CDMC case study, a reduced second-order EV Karnaugh map (K-Map) is analyzed based on gate minimum cover to obtain the sum of product (SOP) output expressions of the CDMC. The generalized output expression for n-bit CDMC is then deduced. The unique product-terms (p-term) of the minimum output expressions are used to construct a p-term table which, are consequently used to programme the FPLA which behaves as a CDMC. A symbolic representation of 8×p×3 CDMC FPLA programmed according to the p-term table is generated. It shows the fusible bit position patterns in both the AND and OR planes.
Authors : Audu, A.I. and Jiya, J.G.
Category : Open Access Volume (Issue) : 10(2) Date Uploaded : 29th October 2024